1. Field of the Invention
The present invention relates to a method for designing a memory embedded semiconductor integrated circuit, which clarifies the conditions that ought to be fulfilled by superior designs/fabrication techniques, and enables selection from a number of techniques the ones suitable to the scales of the memory and the logic circuit during the development of a memory embedded logic LSI, as well as a memory embedded semiconductor integrated circuit as an application of the same method.
2. Description of the Related Art
As memory cells able to be integrated (embedded) in one chip together with logic gates, there exist chiefly SRAM cells and DRAM cells. In addition, there also exist other such types of memory cells, such as three transistor type memory cells, and various nonvolatile memory cells.
The type of memory cell is one of the element techniques that ought to be selected, or ought to be developed when a memory embedded LSI is developed.
However, when a memory embedded LSI is designed or developed, clear criteria does not exist concerning the questions of under what conditions a certain technique is superior to others, and what superior techniques are.
Concerning the memory LSI for exclusive use, such as DRAM, etc., all efforts have been devoted to reducing the cell size provided that the fabrication processes are not made too sophisticated.
On the other hand, for the memory embedded LSI, the consistency with logic processes also should be considered in addition to the balance between reducing the cell area and avoiding the sophistication of fabrication processes, just like the memory LSI for exclusive use.
In practice, because there are not definite criteria about which technique should be selected, in many cases, selections have been made solely relying on the experiences of developers. In addition, when a new element technique is developed, the rich experiences and high degree decisions of the developers are required, for example, to decide definitely where to attain the balance between the cell area and process simplification.
Concerning the development of memory embedded LSI, there also are other subjects in addition to attaining a balance between reducing the cell area and securing the consistency of processes.
For example, in a nonvolatile memory, it is still a problem that should be solved that there are not definite guidelines for attaining the balance between the process consistency and the transistor""s structure parameters and size, which are concerned with the characteristics of high speed transistors used in logic circuit, and high voltage resistance transistors and low voltage resistance transistors used in memory transistors and memory peripheral circuits.
An object of the present invention is to provide a method for designing a memory embedded semiconductor integrated circuit, the same method clarifying the conditions for the element techniques to be technically superior, and making it easy to establish the guideline for selecting the superior techniques, thus enabling easy developments during the development of a memory embedded semiconductor integrated circuit, and to provide a memory embedded semiconductor integrated circuit which fulfills the requirements of technique superiority, as an application of the same method.
According to a first aspect of the present invention, there is provided a method for designing a memory embedded semiconductor integrated circuit having a first region where logic gates are formed, a second region where memory cells are formed, and a third region including all other regions but the first region and the second region, the method comprising the steps of: defining a total resource of a fabrication technique by utilizing various numerical values represented by the process number or mask number required for fabricating the memory embedded semiconductor integrated circuit; deducing a unit resource by dividing the total resource by the effective wafer area; defining a first effective technique resource, a second effective technique resource, and a third effective technique resource by multiplying the unit resource by the area of the first region, the area of the second region, and the area of the third region, respectively; comparing a plurality of techniques concerning fabrication and/or design by using the first to the third effective technique resources obtained as these techniques are employed; and selecting from the plurality of techniques those suitable to the required scales of the memory and the logic circuit.
Preferably, the method comprises the steps of: subtracting the effective technique resources of the technique for comparison from the effective technique resources of the technique under investigation and deducing the differences with respect to each of the first to the third effective technique resources; and adopting the technique under investigation under the condition that the sum of the differences over the first to the third regions is negative.
Specifically, the method comprises the steps of: denoting the following equation (1) by the following procedures;                                                         [                                                                    CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPLG                    ⁡                                          (                      n                      )                                                                      -                                                      CWU                    ⁡                                          (                      i                      )                                                        xc3x97                                      SPLG                    ⁡                                          (                      i                      )                                                                                  ]                        xc3x97            NLG                    +                                    [                              xe2x80x83                            ⁢                                                                    CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      n                      )                                                                      -                                                      CWU                    ⁡                                          (                      i                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      i                      )                                                                                  ]                        xc3x97            NMB                    +                      [                          xe2x80x83                        ⁢                                                            CWU                  ⁡                                      (                    n                    )                                                  xc3x97                SP                ⁢                                  and                                ⁢                                  IO                  ⁡                                      (                    n                    )                                                              -                                                CWU                  ⁡                                      (                    i                    )                                                  xc3x97                SP                ⁢                                  and                                ⁢                                  IO                  ⁡                                      (                    i                    )                                                                        ]                           less than         0                            (        1        )            
by CWU(n) the unit resource obtained by dividing the total resource of the fabrication technique by the effective wafer area when the memory embedded semiconductor integrated circuit is fabricated by using technique N that is under investigation, by CWU(i) the unit resource when performing fabrication using the i-th technique I among a number of m (m: a natural number) techniques that are for comparison, by SPLG(n) the area per logic gate in the first region when technique N is employed, by SPLG(i) the area per logic gate in the first region as technique I is employed, by SPB(n) the area per memory bit in the second region as technique N is employed, by SPB(i) the area per memory bit in the second region as technique I is employed, by SPandIO(n) the area of the third region as technique N is employed, by SPandIO(i) the area of the third region as technique I is employed, by NLG the total number of the logic gates in the first region, and by NMB the total number of the memory bits in the second region; and adopting the technique N under the condition of satisfying the equation (1).
The method comprises a step of adopting the technique N under the condition of satisfying the equation (2), replacing equation (1),                                                         [                              CWU                ⁡                                  (                  n                  )                                            -                              CWU                ⁡                                  (                  i                  )                                                      ]                    xc3x97          SPLG          xc3x97          NLG                +                  "AutoLeftMatch"                      [                                                                                CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      n                      )                                                                      -                                                                            CWU                      ⁡                                              (                        i                        )                                                              xc3x97                                          SPB                      ⁡                                              (                        i                        )                                                                              ]                  xc3x97                  NMB                                +                                  [                                      xe2x80x83                                    ⁢                                                                                    CWU                        ⁡                                                  (                          n                          )                                                                    xc3x97                      SP                      ⁢                                              and                                            ⁢                                              IO                        ⁡                                                  (                          n                          )                                                                                      -                                                                  CWU                        ⁡                                                  (                          i                          )                                                                    xc3x97                      SP                      ⁢                                              and                                            ⁢                                              IO                        ⁡                                                  (                          i                          )                                                                                                      ]                                             less than               0                                                          (        2        )            
when the areas per logic gate SPLG(n) and SPLG(i) being equal, and denoting this area by SPLG.
Furthermore, the method comprises the steps of: denoting the area of the third region by SPandIO when SPandIO(n) is equal to SPandIO(i); and adopting the technique N under the condition of satisfying the equation (3), replacing equation (1),                                                         [                                                                    CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPLG                    ⁡                                          (                      n                      )                                                                      -                                                      CWU                    ⁡                                          (                      i                      )                                                        xc3x97                                      SPLG                    ⁡                                          (                      i                      )                                                                                  ]                        xc3x97            NLG                    +                                    [                              xe2x80x83                            ⁢                                                                    CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      n                      )                                                                      -                                                      CWU                    ⁡                                          (                      i                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      i                      )                                                                                  ]                        xc3x97            NMB                    +                                    [                              xe2x80x83                            ⁢                                                CWU                  ⁡                                      (                    n                    )                                                  -                                  CWU                  ⁡                                      (                    i                    )                                                              ]                        xc3x97            SP            ⁢                          and                        ⁢                          IO              ⁡                              (                                  NLG                  ,                  NMB                                )                                                     less than         0                            (        3        )            
when there are almost not differences in the scales of the logic on board in the first region and in the capacities of the memories on board in the second region, no matter which of technique N and technique I is employed.
On the other hand, the method comprises the steps of: denoting the area of the third region by SPandIO when SPandIO(n) is equal to SPandIO(i); and adopting the technique N under the condition of satisfying the equation (4), replacing equation (2),                                                         [                              CWU                ⁡                                  (                  n                  )                                            -                              CWU                ⁡                                  (                  i                  )                                                      ]                    xc3x97          SPLG          xc3x97          NLG                +                  "AutoLeftMatch"                      [                                                                                CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      n                      )                                                                      -                                                                            CWU                      ⁡                                              (                        i                        )                                                              xc3x97                                          SPB                      ⁡                                              (                        i                        )                                                                              ]                  xc3x97                  NMB                                +                                                      [                                          xe2x80x83                                        ⁢                                                                  CWU                        ⁡                                                  (                          n                          )                                                                    -                                              CWU                        ⁡                                                  (                          i                          )                                                                                      ]                                    xc3x97                  SP                  ⁢                                      and                                    ⁢                                      IO                    ⁡                                          (                                              NLG                        ,                        NMB                                            )                                                                                   less than               0                                                          (        4        )            
when there are almost not differences in the scales of the logic on board in the first region and in the capacities of the memories on board in the second region, no matter which of technique N and technique I is employed.
In the present method for designing a memory embedded semiconductor integrated circuit, the total resource is defined as a quantitative quantity to express the scale of the technique for fabricating the memory embedded semiconductor integrated circuit. Those may be used as the total resource are, for example, the process number and the mask number, etc., which are required for fabricating chips of a memory embedded semiconductor integrated circuit. The total resource also may be defined by using the weighted average process number and mask number, for example, by giving a weight to a mask number according to the process number existing after a certain process that uses masks and before the next process that uses masks.
Next, the resource for fabricating a chip of unit area is deduced by dividing the total resource by the effective wafer area. This resource is called unit resource. The unit resource multiplied by the areas of the first region (logic region), the second region (memory region), or the third region (other region) are the first to the third effective technique resources, respectively.
Then, the technique superiority is compared by employing the first to the third effective technique resources. Specifically, there is a technique N that ought to be investigated; and use I to represent any other existing technique used for comparison. There may be a number of techniques I for comparison. For example, compare technique N under investigation and technique I for comparison by using the first to the third effective technique resources. This comparison result enables the analysis of in what aspects technique N under investigation is superior to technique I for comparison. Namely, since evaluation using the effective technique resources can be performed for each functional block in a memory embedded semiconductor integrated circuit, the technical problems that should be solved and the effects of improvements can be easily estimated.
Next, the effective technique resources as technique I for comparison is employed are subtracted from the effective technique resources as technique N under investigation is employed, and the differences are deduced; for example, the condition for technique N to be adopted is that the sum of these differences is negative. This result enables a easy judgment and selection of a technique N that is superior to technique I for comparison.
According to a second aspect of the present invention, there is provided a memory embedded semiconductor integrated circuit comprising: a first region wherein a logic gate array is formed; a second region; wherein a memory cell array is formed; and a third region other than the first region and the second region, and wherein the circuit fulfills the condition of satisfying the equation (1), that is,                                                         [                                                                    CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPLG                    ⁡                                          (                      n                      )                                                                      -                                                      CWU                    ⁡                                          (                      i                      )                                                        xc3x97                                      SPLG                    ⁡                                          (                      i                      )                                                                                  ]                        xc3x97            NLG                    +                                    [                              xe2x80x83                            ⁢                                                                    CWU                    ⁡                                          (                      n                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      n                      )                                                                      -                                                      CWU                    ⁡                                          (                      i                      )                                                        xc3x97                                      SPB                    ⁡                                          (                      i                      )                                                                                  ]                        xc3x97            NMB                    +                      [                          xe2x80x83                        ⁢                                                            CWU                  ⁡                                      (                    n                    )                                                  xc3x97                SP                ⁢                                  and                                ⁢                                  IO                  ⁡                                      (                    n                    )                                                              -                                                CWU                  ⁡                                      (                    i                    )                                                  xc3x97                SP                ⁢                                  and                                ⁢                                  IO                  ⁡                                      (                    i                    )                                                                        ]                           less than         0                            (        1        )            
where,
CWU(n) denotes the unit resource, which is defined as the division by the effective wafer area of the fabrication technique total resource represented by the process number and/or the mask number required for fabricating the memory embedded semiconductor integrated circuit using technique N that is under investigation,
CWU(i) denotes the unit resource when using for fabrication the ith technique I among a number of m (m: a natural number) techniques that are for comparison,
SPLG(n) is the area per logic gate of the first region as technique N is employed,
SPLG(i) is the area per logic gate of the first region as technique I is employed,
SPB(n) is the area per memory bit of the second region as technique N is employed,
SPB(i) is the area per memory bit of the second region as technique I is employed,
SPandIO(n) is the area of the third region as technique N is employed,
SPandIO(i) is the area of the third region as technique I is employed,
NGL is the total number of the logic gates in the first region, and
NMB is the total number of the memory bits in the second region.